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Internal Clocks
9
Internal Clocks
Table 17. INTERNAL CLOCKS
No.
1
Characteristics
Comparison Frequency
Symbol
Fref 1
Min
5
Typ
—
Max
20
UNIT
MHZ
Condition
Fref = FN/NR
2
Input Clock Frequency
FIN
Fref*NR
NR is input divider
value
3
Output clock Frequency (with
PLL enabled) 2,3
FOUT
75
(1000/Etc × MF x FM)/
(PDF × DF x OD)
—
MHZ
FOUT = FVCO/NO
where NO is output
Tc
13.3
ns
divider value
4
Output clock Frequency (with
FOUT
—
1000/Etc
—
MHZ
—
PLL disabled) 2,3
Tc
5
Duty Cycle
—
40
50
60
%
FVCO=300MHZ
~600MHZ
Note:
1 See users manual for definition.
2 DF = Division Factor
Ef = External frequency
MF = Multiplication Factor
PDF = Predivision Factor
FM= Feedback Multiplier
OD = Output Divider
Tc = internal clock period
3 Maximum frequency will vary depending on the ordered part number.
10
External Clock Operation
The DSP56371 system clock is an externally supplied square wave voltage source connected to EXTAL
(see Figure 4. ).
.
V IH
EXTAL
Midpoint
V IL
ETH
6
ETL
7
8
ETC
Note:
The midpoint is 0.5 (V IH + V IL ).
Figure 4. External Clock Timing
DSP56371 Data Sheet, Rev. 4.1
Freescale Semiconductor
37
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